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| Si4022 Universal ISM Band FSK Transmitter DESCRIPTION Integration's Si4022 is a single chip, low power, multi-channel FSK transmitter designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the bands at 868 and 915 MHz. Used in conjunction with Integration's FSK receivers, it is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated. Only an external crystal and bypass filtering is needed for operation. The transmitter has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL's high resolution allows the usage of multiple channels in any of the bands. In addition, highly stable and accurate FSK modulation is accomplished by direct closed-loop modulation with bit rates up to 115.2 kbps. The integrated power amplifier of the transmitter has an open-collector differential output and can directly drive a loop antenna with programmable output level, no additional matching network is required. An automatic antenna tuning circuit is built in to avoid both costly trimming procedures and de-tuning due to the "hand effect". For battery-operated applications the device supports various power saving modes with wake-up interrupt generation options based on a low battery voltage detector and a sleep timer. Several additional features ease system design. Power-on reset and clock signals are provided to the microcontroller. An on-chip baud rate generator and a data FIFO are available. The transmitter is programmed and controlled via an SPI compatible interface. SDI SCK nSEL SDO nIRQ CLK VREFO VSS_D 1 2 3 4 5 6 7 8 Si4022 PIN ASSIGNMENT 16 15 14 13 12 11 10 9 FSK VDD VSS_B RF02 RF01 VSS_A nRES XTL / REF This document refers to Si4022-IC Rev A0. See www.silabs.com/integration for any applicable errata. See back page for ordering information. FEATURES * * * * * * * * * * * * * * * * * * * * * Fully integrated (low BOM, easy design-in) No alignment required in production Fast settling, programmable, high-resolution PLL Fast frequency hopping capability Stable and accurate FSK modulation with programmable deviation Programmable PLL loop bandwidth Direct loop antenna drive Automatic antenna tuning circuit Programmable output power level SPI bus for interfacing with microcontroller Clock and reset signals for microcontroller 64 bit TX data FIFO Integrated programmable crystal load capacitor Standard 10 MHz crystal reference Power-saving modes Multiple event handling options for wake-up activation Wake-up timer Low battery detection 2.2 to 3.8 V supply voltage Low power consumption Low standby current (typ. 0.3 A) FUNCTIONAL BLOCK DIAGRAM XTL 9 CRYSTAL OSCILLATOR REFERENCE 13 RF02 RF01 SYNTHESIZER 12 CLOCK FREQUENCY LOAD CAP LEVEL 6 CLK nIRQ SDO SDI SCK nSEL FSK VDD VSS_A VDD_B VSS_D VREFO 15 11 LOW BATTERY DETECT LOW BAT TRESHOLD CONTROLLER 5 4 1 2 TYPICAL APPLICATIONS * * * * * * * * * Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy control Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading 14 8 7 TIMEOUT WAKE -UP TIMER 3 PERIOD 16 10 nRES 1 IA4222-DS rev 1.1r 0308 www.silabs.com/integration i Si4022 DETAILED FEATURE-LEVEL DESCRIPTION The Si4022 FSK transmitter is designed to cover the unlicensed frequency bands at 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. Low Battery Voltage Detector The low battery detector circuit monitors periodically (typ. 8 ms) the supply voltage and generates an interrupt if it falls below a programmable threshold level. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL's high resolution allows the usage of multiple channels in any of the bands. The FSK deviation is selectable (from 20 to 160 kHz with 20 kHz increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is also highly accurate due to the direct closed-loop modulation of the PLL. The transmitted digital data can be sent asynchronously through the FSK pin or over the control interface using the appropriate command. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. To ensure proper operation in the programmed frequency band, the RF VCO is automatically calibrated upon activation of the synthesizer. Wake-Up Timer The wake-up timer has very low current consumption (4 A max) and can be programmed from 1 ms to several hours. It calibrates itself to the crystal oscillator at every startup and then at every 40 seconds with an accuracy of 0.5%. When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. The periodic autocalibration feature can be turned off. Event Handling In order to minimize current consumption, the transmitter supports the sleep mode. Switching between the various modes is controlled by the appropriate bits in the Power Management Command (page 11). Si4022 generates an interrupt signal on several events (wakeup timer timeout, low supply voltage detection, on-chip FIFO almost empty). This signal can be used to wake up the microcontroller, ef fectively reducing the period the microcontroller has to be active. The cause of the interrupt can be read out from the receiver by the microcontroller through the SDO pin. RF Power Amplifier (PA) The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called "hand effect." Crystal Oscillator and Microcontroller Clock Output The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transmitter can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. In normal operation it is divided from the reference 10 MHz. During sleep mode a low frequency (typical 32 kHz) output clock signal can be switched on. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Power Management Command, the chip provides a certain number (default is 128) of further clock pulses ("clock tail") for the microcontroller to let it go to idle or sleep mode. Interface and Controller An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the output power. Division ratio for the microcontroller clock, wakeup timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transmitter. 2 Si4022 PIN DEFINITION Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output SDI SCK nSEL SDO nIRQ CLK VREFO VSS_D 1 2 3 4 5 6 7 8 16 15 14 FSK VDD VSS_B RF02 RF01 VSS_A nRES XTL / REF IA4222 13 12 11 10 9 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name SDI SCK nSEL SDO nIRQ CLK VREFO VSS_D XTL / REF Function SDI SCK nSEL SDO nIRQ CLK VREFO VSS_D XTL REF Type DI DI DI DO DO DO AO S AIO DI DO S AO AO S S DI Serial control / data input Serial interface clock input Description Chip (interface) select input (active low) Serial status data output Interrupt request output (active low) Clock output for the microcontroller Voltage reference output Negative supply voltage (digital) Crystal connection (other terminal of crystal to VSS) External reference input Reset output (active low) Negative supply voltage (analog) RF differential signal output (open collector) RF differential signal output (open collector) Negative supply voltage (bulk) Positive supply voltage Data input for asynchronous modulation nRES VSS_A RFO1 RFO2 VSS_B VDD FSK nRES VSS_A RFO1 RFO2 VSS_B VDD FSK 3 Si4022 GENERAL DEVICE SPECIFICATION All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Vdd Vin Iin ESD Tst Tld Parameter Positive supply voltage Voltage on any pin Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature Lead temperature (soldering, max 10 s) Min -0.5 -0.5 -25 Max 6.0 Vdd+0.5 25 1000 Units V V mA V o o -55 125 260 C C Recommended Operating Range Symbol Vdd Top Parameter Positive supply voltage Ambient operating temperature Min 2.2 -40 Max 3.8 +85 Units V o C ELECTRICAL SPECIFICATION (Min/max values are valid over the whole recommended operating range, typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V) DC Characteristics Symbol Idd,TX0 Idd,TXmax Ipd Ilb Ix Vlb Vlba VPOR Parameter Supply current Supply current Standby current (Note 1) Low battery voltage detector and wake-up timer current Idle current Low battery detection threshold Low battery detection accuracy Vdd threshold required to generate a POR POR hysteresis Vdd slew rate Conditions/Notes 868 MHz band, Pout = 0dBm 915 MHz band, Pout = 0dBm 868 MHz band, Pout = Pmax 915 MHz band, Pout = Pmax all blocks disabled Min Typ 14 15 23 24 1 Max Units mA mA A 5 crystal oscillator is ON programmable in 0.1 V steps 2.0 0.05 1.5 larger glithches on the Vdd generate a POR even above the threshold VPOR for proper POR generation 0.1 0.5 3.5 A mA V V V VPOR,hyst SRVdd 0.6 V V/ms Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period for sending 100 bytes packets in length at 19.2 kbps with +6 dBm output power in the 915 MHz band. 4 Si4022 DC Characteristics (continued) Symbol Vil Vih Iil Iih Vol Voh Parameter Digital input low level Digital input high level Digital input current Digital input current Digital output low level Digital output high level Conditions/Notes Min 0.7*Vdd Typ Max 0.3*Vdd Units V V Vil = 0 V Vih = Vdd, Vdd = 3.8 V Iol = 2 mA Ioh = -2 mA -1 -1 1 1 0.4 A A V V Vdd-0.4 AC Characteristics Symbol fLO fref fres tlock tsp Cxl tPOR tsx tPBt twake-up Parameter Transmitter frequency PLL reference frequency PLL frequency resolution PLL lock time PLL startup time Crystal load capacitance, see crystal selection guide Internal POR pulse width (Note 2) Crystal oscillator startup time Wake-up timer clock period Programmable wake-up time Conditions/Notes 868 MHz band, 20 kHz resolution 915 MHz band, 20 kHz resolution (Note 1) Min 801.92 881.92 9 Typ Max 878.06 958.06 Units MHz MHz kHz s 10 20 11 Frequency error < 1kHz after 1 MHz step Initial calibration after power-up with running crystal oscillator Programmable in 0.5 pF steps, tolerance +/- 10% After Vdd has reached 90% of final value Crystal ESR < 100 Calibrated every 40 seconds (Note 3) 0.995 1 8.5 30 500 16 50 2 1 100 5 1.005 8.4*106 s pF ms ms ms ms Note 1: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency parameters will change accordingly. Note 2: No command are accepted by the chip during this period. Note 3: Autocalibration can be turned off. 5 Si4022 AC Characteristics (continued) Symbol BR Iout Pmax Pout Psp Cout Qout Lout Cin, D tr, f tr, f ,ckout fckout, slow Parameter FSK bit rate Open collector output current Available output power Typical output power Spurious emission Output capacitance Quality factor of the output capacitance Output phase noise Digital input capacitance Digital output rise/fall time Clock output rise/fall time Slow clock frequency Conditions/Notes (Note 4) Adjustable in 8 steps With optimal antenna impedance (Note 5) Adjustable in 8 steps (3 dB/step) Out of band, EIRP (Note 6) Set by the automatic antenna tuning circuit Min 0.5 Typ Max 115.2 6 Units kbps mA dBm 6 Pmax - 21 Pmax -52 1.6 16 2.2 18 -85 -105 2 2.8 22 dBm dBm pF 100 kHz from carrier 1 MHz from carrier (Note 4) dBc/Hz pF ns ns kHz 15 pF pure capacitive load 10 pF pure capacitive load Tolerance +/- 1 kHz 32 10 15 Setting (bw1, bw0) 00 01 10 11 Max. datarate [kbps] 19.2 38.4 64 115.2 Phase noise at 1 MHz offset [dBc/Hz] -112 -110 -107 -102 PLL bandwidth 15 kHz 30 kHz 60 kHz (POR default) 120 kHz Band 868 MHz 915 MHz Y antenna [S] 1.35E-3 - j1.2E-2 1.45E-3 - j1.3E-2 Z antenna [] 9 + j82 8.7 + j77 L antenna [nH] 15.2 13.6 Note 4: The maximum FSK bitrate and the output phase noise are dependent on the PLL settings (with the Extended Features Command). Note 5: Optimal antenna / admittance / inductance for the Si4022 Note 6: With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration). 6 Si4022 TYPICAL PERFORMANCE DATA Phase noise measurements in the 868 MHz ISM band 50% Charge pump current setting (Ref. level: -60 dBc/Hz, 10 dB/div) 11:52:47 May 5, 2005 Carrier Power -11.11 dBm Atten Ref -60.00dBc/Hz 10.00 1 dB/ 0.00 dB Phase Noise 100, 50, 33% Charge pump current settings (Ref. level: -70 dBc/Hz, 5 dB/div) 13:30:49 May 5, 2005 Phase Noise 0.00 dB L Mkr4 5.00800 MHz -115.65 dBc/Hz L Mkr1 1.00000 MHz -101.95 dBc/Hz Carrier Power -11.03 dBm Atten Ref -70.00dBc/Hz 5.00 dB/ 2 3 4 1 2 3 10 kHz Marker 1 2 3 4 Frequency Offset Type Spot Spot Spot Spot Freq Freq Freq Freq 10 MHz X Axis 10 151 1 5.008 kHz kHz MHz MHz -76.65 -86.95 -107.11 -115.65 10 kHz Marker 1 2 3 Frequency Offset Type Spot Freq Spot Freq Spot Freq 10 MHz X Axis 1 MHz 1 MHz 1 MHz Trace 2 2 2 2 Value dBc/Hz dBc/Hz dBc/Hz dBc/Hz Trace 1 2 3 Value -101.95 dBc/Hz -107.05 dBc/Hz -109.98 dBc/Hz Unmodulated RF Spectrum The output spectrum is measured at different frequencies. The output is loaded with 50 Ohm through a matching network. At 868 MHz 10:26:50 May 5, 2005 Ref 0 dBm Samp Log 10 dB/ Atten 10 dB 1 At 915 MHz L Mkr1 868.0010 MHz -12.2 dBm Ref 0 dBm Samp Log 10 dB/ 10:34:57 May 5, 2005 Atten 10 dB 1 L Mkr1 915.0020 MHz -14.09 dBm VAvg 100 W1 S2 S3 FC AA VAvg 100 W1 S2 S3 FC AA Center 868 MHz Res BW 10 kHz VBW 10 kHz Span 2 MHz Sweep 40.74 ms (2001 pts) Center 915 MHz Res BW 10 kHz VBW 10 kHz Span 2 MHz Sweep 40.74 ms (2001 pts) 7 Si4022 At 868 MHz with 180 kHz Deviation at 9.6 kbps 11:14:40 May 5, 2005 Ref 0 dBm Samp Log 10 dB/ Atten 10 dB L VAvg 100 W1 S2 S3 FC AA Center 868 MHz Res BW 10 kHz VBW 10 kHz Span 2 MHz Sweep 40.74 ms (2001 pts) Antenna Tuning Characteristics 750-970 MHz The antenna tuning characteristics was recorded in "max-hold" state of the spectrum analyzer. During the measurement, the transmitters were forced to change frequencies by forcing an external reference signal to the XTL pin. While the carrier was changing the antenna tuning circuit switched trough all the available states of the tuning circuit. The graph clearly demonstrates that while the complete output circuit had about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words the tuning circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread. 8 Si4022 CONTROL INTERFACE Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer multiple of 8 (except for the Transmitter FIFO Write Command). All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don't care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. Timing Specification Symbol tCH tCL tSS tSH tSHI tDS tDH tOD Parameter Clock high time Clock low time Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time Minimum value [ns] 25 25 10 10 25 5 5 10 Timing Diagram tSS nSEL tCH tCL tOD tSH tSHI SCK tDS SDI tDH BIT15 BIT14 BIT13 BIT8 BIT7 BIT1 BIT0 SDO BIT15 BIT14 BIT13 BIT8 BIT7 BIT1 BIT0 9 Si4022 Control Commands Control Word Configuration Setting Command Frequency Setting Command Power Managament Command Transmitter FIFO Write Command FIFO Setting Command Data Rate Command Low Battery and Microcontroller Clock Divider Command Wake-up Timer Command Extended Wake-up Timer Command Extended Features Command Status Register Read Command Related Parameters/Functions frequency band and deviation, output power, crystal oscillator load capacitance frequency of the local oscillator crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer, clock output buffer transmitter FIFO write FIFO functions bit rate LBD voltage threshold and microcontroller clock division ratio wake-up time period wake-up time period finer adjustment low frequency output clock, wake-up timer extra functions transmitter status read Note: Note In the following tables the POR column shows the default values of the command registers after power-on. Configuration Setting Command bit 15 1 14 0 13 0 12 1 11 bs 10 p2 9 p1 8 p0 7 x3 6 x2 5 x1 4 x0 3 ms 2 m2 1 m1 0 m0 POR 9082h bs 0 1 Frequency Band [MHz] 868 915 x3 x2 0 0 0 0 ...... 1 1 1 1 1 1 0 1 x1 0 0 1 1 x0 0 1 0 1 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 .... 15.5 16.0 p2 0 0 0 0 1 1 1 1 p1 0 0 1 1 0 0 1 1 p0 0 1 0 1 0 1 0 1 Output Power [dBm] 0 -3 -6 -9 -12 -15 -18 -21 0 0 0 0 The output power is given in the table as relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note available from http://www.silabs.com/integration). The resulting output frequency can be calculated as: fout = f0 - (-1)SIGN * (M + 1) * (20 kHz) where: f0 is the channel center frequency (see the next command) M is the three bit binary number 10 Si4022 Frequency Setting Command bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR AD57h The 12-bit parameter of the Frequency Setting Command The constant C is determined by the selected band as: Band [MHz] 868 915 C 10 11 Power Management Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 ex 4 es 3 etr 2 eb 1 et 0 dc POR C002h Bit 5 Enables the the crystal oscillator. Enables the synthesizer. Enables the power amplifier. If the ex and es bit is not set, it switches on the crystal oscillator and the synthesizer as well. In FIFO mode (bit fe is set in the FIFO Setting Command) setting this bit will roll out the content of the FIFO. Enables the low battery detector. Enables the wake-up timer. Disables the clock output buffer. Bit 2 If faster operation is needed, then leave ex and es bit set to `1' and toggle only the etr bit. Power Saving Modes The different operating modes of the chip depend on the following control bits: Operating Mode Active (transmit) Idle Sleep Standby eb or et X X 1 0 es x 0 0 0 etr 1 0 0 0 ex x 1 0 0 Transmitter FIFO Write Command Bit 7 1 6 1 5 0 4 0 3 0 2 1 1 1 0 0 POR - With this command, the controller can write databits to the transmitter FIFO. Bit (fe) must be set in the FIFO Setting Command. 11 Si4022 Transmitter FIFO register write nSEL 0 SCK instruction filling up FIFO 1 2 3 4 5 6 7 0 1 2 3 4 5 N-2 N-1 SDI N data bits Data Transmit Sequence Through the FSK Pin It is possible to transmit data without the FIFO by using the FSK input pin. In that case the power amplifier should be enabled first with the Power Management Comand. nSEL Power Management command C0h SCK instruction SDI 38h tsx * Internal operations ex, es, etr = 1 Xtal osc staus tsp * synthesizer / PLL / PA status synthesizer on, PLL locked, PA ready to transmit xtal osc. stable FSK don't care TX DATA NOTE: * See page 5 for the timing values Note: * If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs tsx time, to switch on. The actual value depends on the type of quartz crystal used. * If the synthesizer was formerly switched off (es=0), the internal PLL needs tsp startup time. Valid data can be transmitted only when the internal locking process is finished. FIFO Setting Command bit 15 1 14 1 13 0 12 0 11 1 10 1 9 1 8 0 7 fe 6 0 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR CE00h Bit 7 Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO. FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this level. 12 Si4022 Data Rate Command bit 15 1 14 1 13 0 12 0 11 1 10 0 9 0 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C813h The bit rate of the transmitted data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs. BR = 10 MHz / 29 / (R+1) / (1 + cs*7) In the receiver set R according the next function: R= (10 MHz / 29 /(1 + cs*7)/ BR) - 1 Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Low Battery and Microcontroller Clock Divider Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 d2 6 d1 5 d0 4 elfc 3 t3 2 t2 1 t1 0 t0 POR C213h The 4-bit value T of t3-t0 determines the threshold voltage of the threshold voltage Vlb of the detector: Vlb= 2.0 V + T * 0.1 V Bit 4 d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [MHz] 1 1.25 1.66 2 2.5 3.33 5 10 Wake-Up Timer Command bit 15 1 14 1 13 1 12 0 11 r3 10 r2 9 r1 8 r0 7 m7 6 m6 5 m5 4 m4 3 m3 2 m2 1 m1 0 m0 POR E196h The wake-up time period can be calculated by M Note:* Note The wake-up timer generates interrupts continuously at the programmed interval while the et bit is set. Extended Wake-Up Timer Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 1 7 d1 6 d0 5 m13 4 m12 3 m11 2 m10 1 m9 0 m8 POR C300h These bits can be used for further fine adjustment of the wake-up timer. The explanation of the bits can be found above. 13 Si4022 Extended Features Command: bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 exlp 6 ctls 5 0 4 dcal 3 bw1 2 bw0 1 dsfi 0 ewi POR B0CAh Bit 7 Enables low power mode for the crystal oscillator. Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128. Disables the wake-up timer autocalibration. Bit 3-2 bw1 0 0 1 1 bw0 0 1 0 1 PLL bandwidth 15 kHz 30 kHz 60 kHz 120 kHz Bit 1 Disables autosleep on FIFO interrupt if set to 1. Enables the automatic wake-up on any interrupt event. Status Register Read Command bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POR - With this command, it is possible to read the status register of the chip through the SDO pin. FFIT FFEM FFOV LBD WK-UP POR The number of data bits in the FIFO has gone below the preprogrammed limit FIFO is empty FIFO overflow Low battery detect, the power supply voltage is below the preprogrammed limit Wake-up timer overflow Power-on reset Status Register Read Sequence nSEL 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDI status out SDO FFIT FFEM FFOV LBD WK-UP POR 14 Si4022 Dual Clock Output When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz clock signal is available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the Low Battery and Microcontroller Clock Divider Command (page13). During startup and in sleep or standby mode (crystal oscillator disabled), the CLK output is pulled to logic low. On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the Low Battery and Microcontroller Clock Divider Command. The clock frequency is 32 kHz which is derived from the low-power RC oscillator of the wake-up timer. In order to use this slow clock the wake-up timer should be enabled by setting the et bit in the Power Management Command (page 11) even if the wakeup timer itself is not used. Slow clock feature can be enabled by entering into sleep mode (page 11). Driving the output will increase the sleep mode supply current. Actual worst-case value can be determined when the exact load and min/max operating conditions are defined. After poweron reset the chip goes into sleep mode and the slow frequency clock appears on the CLK pin. Switching back into fast clock mode can be done by setting the ex or etr bits in the approriate commands. It is important to leave bit dc in the Power Management Command at its default state (0) otherwise there will be no clock signal on the CLK pin. Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at least a half cycle of the fast clock. During switching the clock can be logic low once for an intermediate period i.e. for any time between the half cycle of the fast and the slow clock. Tslow slow clock fast clock output clock periods are not to scale 0.5 * Tfast < Tx < 0.5 * Tslow Tx Tfast The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of 0 to Tslow + Tfast from the occurrence of a clock change request (entering into sleep mode or interrupt) until the beginning of the intermediate length (Tx) half cycle. The other is that both clocks should be up and running for the change to occur. Changing from fast to slow clock, it is automatically ensured by entering into the sleep mode in the appropriate way provided that the wake-up timer is continouosly enabled. As the crystal oscillator is normally stopped while the slow clock is used, when changing back to fast clock the crystal oscillator startup time has to pass first before the above mentioned latency period starts. The startup condition is detected internally, so no software timing is necessary. Wake-Up Timer Calibration By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Power Management Command. After timeout the timer can be stopped by resetting this bit otherwise it operates continuously. If the timer is programmed to run for longer periods, at approximately every 40 seconds it performs additional self-calibration. This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software algorithm can then compensate for the gradual shift caused by temperature change. Bit dcal in the Extended Features Command (page 14) controls the automatic calibration feature. It is reset to 0 at power-on and the automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit to 1. 15 Si4022 MATCHING NETWORK FOR A 50 OHM SINGLE ENDED OUTPUT Matching Network Schematic VDD L3 to RFP 50 Ohm load GND to RFN C1 , C2 [pF] L1 [nH] L3 [nH] 3.9 6.8 100 C1 L1 C2 GND RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). 16 Si4022 CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4022 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. It is recommended to keep the PCB parasitic capacitances on the XTL pin as low as possible. The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency (fc). Therefore fc is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable carrier frequency error. Maximum XTAL Tolerances Including Temperature and Aging [ppm] Bit Rate: 2.4 kbps 20 868 915 2 2 40 12 12 60 25 20 Transmitter Deviation [+/- kHz] 80 30 30 100 40 40 120 50 50 140 70 60 160 80 70 Bit Rate: 9.6 kbps 20 868 915 do not use do not use 40 8 8 60 20 15 Transmitter Deviation [+/- kHz] 80 30 30 100 40 40 120 50 50 140 60 60 160 70 70 Bit Rate: 38.4 kbps 20 868 915 40 60 10 10 Transmitter Deviation [+/- kHz] 80 20 20 100 30 30 120 40 40 140 50 50 160 70 60 do not use do not use do not use do not use Bit Rate: 115.2 kbps 20 868 915 40 60 Transmitter Deviation [+/- kHz] 80 100 120 2 2 140 12 12 160 25 20 do not use do not use do not use do not use do not use do not use do not use do not use do not use do not use Whenever a low frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the "midrange", for example 16 pF. The "pull-ability" of the crystal is defined by its motional capacitance and C0. Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or channel separations. 17 Si4022 EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION Data packet structure An example data packet structure using theSi4022 -Si4022 pair for data transmission. This packet structure is an example of how to use the high efficiency FIFO mode at the receiver side: AA AA AA 2D D4 D 0 D 1 D 2 ... DN Prea mble Databytes (received in the FIFO of the receive r) Synchron pattern The first 3 bytes compose a 24 bit length `01' pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes compose a 16 bit synchron pattern which is essential for the receiver's FIFO to find the byte synchron in the received bit stream. The synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D0 in the picture above) will be the first received byte in the FIFO. Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side will be unable to track. Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual. 18 Si4022 PACKAGE INFORMATION 16-pin TSSOP 19 Si4022 ORDERING INFORMATION Si4022 Universal ISM Band FSK Transmitter DESCRIPTION Si4022 16-pin TSSOP die ORDERING NUMBER Si4022-IC CC16 see Silicon Labs Rev A0 Demo Boards and Development Kits DESCRIPTION ISM Chipset Development Kit ORDERING NUMBER IA ISM - DK3 Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide IA4322 Universal ISM Band FSK Receiver ORDERING NUMBER IA ISM - AN1 IA ISM - AN2 see http://www.silabs.com/integration for details Note: Volume orders must include chip revision to be accepted. Silicon Labs, Inc. 400 West Cesar Chavez Austin, Texas 78701 Tel: 512.416.8500 Fax: 512.416.9669 Toll Free: 877.444.3032 www.silabs.com/integration wireless@silabs.com The specifications and descriptions in this document are based on information available at the time of publication and are subject to change without notice. Silicon Laboratories assumes no responsibility for errors or omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes to the product and its documentation at any time. Silicon Laboratories makes no representations, warranties, or guarantees regarding the suitability of its products for any particular purpose and does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability for consequential or incidental damages arising out of use or failure of the product. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Silicon Laboratories or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. (c)2008 Silicon Laboratories, Inc. All rights reserved. Silicon Laboratories is a trademark of Silicon Laboratories, Inc. All other trademarks belong to their respective owners. 20 |
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